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1 ps9038c 06/29/10 enable1 bclk[0:4] bclk5 5 sync sync enable2 xtal_in xtal_out block diagram PI6C10806B 1.8v/2.5v/3.3v, 100mhz, low skew 1:6 crystal to lvcmos clock buffer description pericom semiconductors PI6C10806B is a low skew six output crystal oscillator driver. crystal oscillator input range is from 10mhz to 50mhz. if xtal_in is driven with a signal source, then the input frequency can be as high as 100mhz. PI6C10806B, the outputs are confgured into 2 groups: a fve output and a single output; each with independent output enable. PI6C10806B has a wide range of operating voltages: 1.8v, 2.5v, and 3.3v. this feature paired with the low output-to-output and part-to- part skew makes the device ideal for low voltage, low power, high frequency single ended applications; such as networking features ? six low skew outputs: < 80ps ? crystal oscillator input: 10mhz to 50mhz ? switching frequency up to 100 mhz ? fast output rise/fall time: < 800ps ? synchronous output enables ? industrial temperature range: C40c to +85c ? 1.8v , 2.5v and 3.3v operation C mixed 3.3v core/2.5v output, 3.3v core/1.8v output, and 2.5v core/1.8v output operating voltages ? packaging (pb-free & green available): C 16-pin 173-mil wide tssop (l) pin description pin name description enable1, enable2 active high output enable inputs xtal_in crystal interface xtal_out crystal interface bclk[0:5] clock outputs gnd ground v dd core power v ddo output power truth table (1) inputs outputs enable1 enable2 bclk[0:4] bclk5 l l l l l h l switching h l switching l h h switching switching note: 1. h = high voltage level, l = low voltage level xtal_in xtal_out 1 16 enable1 enable2 2 15 bclk5 gnd 3 14 bclk4 bclk0 4 13 v ddo v ddo 5 12 gnd bclk1 6 11 bclk3 gnd 7 10 v dd bclk2 8 9 pin confguration 10-0151
2 ps9038c 06/29/10 PI6C10806B 1.8v/2.5v/3.3v, 100mhz, low skew 1:6 crystal to lvcmos clock buffer power supply dc characteristics ( v dd / v ddo = 3.3v 5%, t a = -40c to 85c) symbols parameters test conditions min. typ max. units v dd core supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current enable1:2 = '00' 10 ma i ddo output supply current enable1:2 = '00' 5 ma power supply dc characteristics ( v dd / v ddo = 2.5v 5%, t a = -40c to 85c) symbols parameters test conditions min. typ max. units v dd core supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current enable1:2 = '00' 8 ma i ddo output supply current enable1:2 = '00' 4 ma power supply dc characteristics ( v dd / v ddo = 1.8v 0.2v, t a = -40c to 85c) symbols parameters test conditions min. typ max. units v dd core supply voltage 1.6 1.8 2.0 v v ddo output supply voltage 1.6 1.8 2.0 v i dd power supply current enable1:2 = '00' 5 ma i ddo output supply current enable1:2 = '00' 3 ma power supply dc characteristics ( v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = -40c to 85c) symbols parameters test conditions min. typ max. units v dd core supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current enable1:2 = '00' 10 ma i ddo output supply current enable1:2 = '00' 4 ma power supply dc characteristics ( v dd = 3.3v 5%, v ddo = 1.8v 0.2v, t a = -40c to 85c) symbols parameters test conditions min. typ max. units v dd core supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 1.6 1.8 2.0 v i dd power supply current enable1:2 = '00' 10 ma i ddo output supply current enable1:2 = '00' 3 ma 10-0151
3 ps9038c 06/29/10 PI6C10806B 1.8v/2.5v/3.3v, 100mhz, low skew 1:6 crystal to lvcmos clock buffer power supply dc characteristics ( v dd = 2.5v 5%, v ddo = 1.8v 0.2v, t a = -40c to 85c) symbols parameters test conditions min. typ max. units v dd core supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 1.6 1.8 2.0 v i dd power supply current enable1:2 = '00' 8 ma i ddo output supply current enable1:2 = '00' 3 ma i/o dc characteristics (t a = -40c to 85c) symbols parameters test conditions min. typ max. units v ih input high voltage enable 1, enable 2 v dd = 3.3v 5% 2 v ddo + 0.3 v v dd = 2.5v 5% 1.7 v ddo + 0.3 v v dd = 1.8v 0.2v 1.65* v ddo v ddo + 0.3 v v il input low voltage enable 1, enable 2 v dd = 3.3v 5% -0.3 0.8 v v dd = 2.5v 5% -0.3 0.7 v v dd = 1.8v 0.2v -0.3 0.35* v ddo v v oh output high voltage v ddo = 3.3v 5% (1) 2.6 v v ddo = 2.5v 5%; i oh = -1ma 2 v v ddo = 2.5v 5% (1) 1.8 v v ddo = 1.8v 0.2v (1) v ddo - 0.3 v v ol output low voltage v dd = 3.3v 5% (1) 0.5 v v ddo = 2.5v 5%; i oh = -1ma 0.4 v v ddo = 2.5v 5% (1) 0.45 v v ddo = 1.8v 0.2v (1) 0.35 v notes: 1. for max. or min. conditions, use appropriate operating v dd and t a values. 10-0151
4 ps9038c 06/29/10 PI6C10806B 1.8v/2.5v/3.3v, 100mhz, low skew 1:6 crystal to lvcmos clock buffer storage temperature ........................................................... C65c to +150c v dd, v ddo voltage ............................................................... C0.5v to +3.6v output voltage (max. 4.6v) .......................................... C0.5v to v dd +0.5v input voltage (max 4.6v) .............................................. C0.5v to v dd +0.5v 3.3v absolute maximum ratings (above which the useful life may be impaired. for user guidelines only , not tested.) note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect reliability. 3.3v i/o dc characteristics (over operating range: v dd = 3.3v 5%, t a = -40 to 85c) parameters description test conditions (1) min. typ. (2) max. units v ddo i/o supply voltage 3.135 3.3 3.465 v ih input high voltage logic high level 2 v dd +0.3 v v il input low voltage logic low level -0.3 1.3 v oh output high voltage v ddo = min., v in = v ih or v il i oh = -1ma 2 v i oh = -8ma 2 v ol output low voltage v ddo = min., v in = v ih or v il i ol = 1ma 0.4 i ol = 8ma 0.4 notes: 1. for max. or min. conditions, use appropriate operating range values. 2. t ypical values are at v dd =3.3v, +25c ambient and maximum loading. 3.3v i/o ac characteristics (over operating range: v dd /v ddo = 3.3v 5%, t a = -40 to 85c) parameters description test conditions (1) min. typ max. units f out output frequency using crystal 10 50 mhz external clock (2) 0 100 t dc output duty cycle @ v ddo /2 47 53 % t r /t f clkn rise/fall time 20% to 80% 150 800 ps rms random rms phase jitter 25mhz @ integration range 100hz - 1mhz 0.098 ps t sk(o) (3) output to output skew between any two outputs of the same device @ same transition @v ddo /2 80 ps t dis, t en ( 4) output enable/disable @v ddo /2 4 cycles notes: 1. unless noted otherwise, all parameters are tested with xtal @ f <= fxtal_max,; outputs are terminated @ 50? to v ddo /2 , see waveforms. 2. external clock source is driving xt al_in input 3. identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 4. these parameters are guaranteed, but not tested. max delay is 4 cycles. min. setup time = 3ns. 10-0151
5 ps9038c 06/29/10 PI6C10806B 1.8v/2.5v/3.3v, 100mhz, low skew 1:6 crystal to lvcmos clock buffer storage temperature ........................................................... C65c to +150c v dd, v ddo voltage ............................................................... C0.5v to +3.6v output voltage (max. 3.6v) .......................................... C0.5v to v dd +0.5v input voltage (max 3.6v) .............................................. C0.5v to v dd +0.5v 2.5v absolute maximum ratings (above which the useful life may be impaired. for user guidelines only , not tested.) note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect reliability. 2.5v i/o dc characteristics (over operating range: v dd = 2.5v 5%, t a = -40 to 85c) parameters description test conditions (1) min. typ. (2) max. units v ddo i/o supply voltage 2.375 2.5 2.625 v ih input high voltage logic high level 1.7 v dd +0.3 v v il input low voltage logic low level -0.3 0.7 v oh output high voltage v ddo = min., v in = v ih or v il i oh = -1ma 2 v i oh = -8ma 2 v ol output low voltage v ddo = min., v in = v ih or v il i ol = 1ma 0.4 i ol = 8ma 0.4 notes: 1. for max. or min. conditions, use appropriate operating range values. 2. t ypical values are at v dd =3.3v, +25c ambient and maximum loading. 2.5v i/o ac characteristics (over operating range: v dd /v ddo = 2.5v 5%, t a = -40 to 85c) parameters description test conditions (1) min. typ max. units f out output frequency using crystal 10 50 mhz external clock (2) 0 100 t dc output duty cycle @ v ddo /2 47 55 % t r /t f clkn rise/fall time 20% to 80% 150 800 ps rms random rms phase jitter 25mhz @ integration range 100hz - 1mhz 0.112 ps t sk(o) (3) output to output skew between any two outputs of the same device @ same transition @v ddo /2 80 ps t dis, t en ( 4) output enable/disable @v ddo /2 4 cycles notes: 1. unless noted otherwise, all parameters are tested with xtal @ f <= fxtal_max,; outputs are terminated @ 50? to v ddo /2 , see waveforms. 2. external clock source is driving xt al_in input 3. identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 4. these parameters are guaranteed, but not tested. max delay is 4 cycles. min. setup time = 3ns. 10-0151
6 ps9038c 06/29/10 PI6C10806B 1.8v/2.5v/3.3v, 100mhz, low skew 1:6 crystal to lvcmos clock buffer 1.8v i/o dc characteristics (over operating range: v ddo = 1.8v 0.2v, t a = -40 to 85c) parameters description test conditions (1) min. typ. (2) max. units v ddo i/o supply voltage 1.6 1.8 2.0 v v ih input high voltage logic high level 0.65*v dd v dd +0.3 v il input low voltage logic low level -0.3 0.35*v dd i l input current v dd = max, v in = v dd or gnd i pin 15 a v oh output high voltage v dd = min., v in = v ih or v il i oh = -2ma 1.2 v i oh = -8ma 1.2 v ol output low voltage v dd = min., v in = v ih or v il i ol = 2ma 0.35 i ol = 8ma 0.35 notes: 1. for max. or min. conditions, use appropriate operating v dd and ta values. 2. t ypical values are at v dd = 1.8v, +25c ambient and maximum loading. storage temperature ........................................................... C65c to +150c v ddo ,v dd voltage ................................................................ C0.5v to +2.5v output voltage (max 2.5v) .......................................... C0.5v to v dd +0.5v input voltage (max 2.5v) ............................................. C0.5v to v dd +0.5v 1.8v absolute maximum ratings (above which the useful life may be impaired. for user guidelines only , not tested.) note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect reliability. 1.8v i/o ac characteristics (over operating range: v dd / v ddo = 1.8v 0.2v, t a = -40 to 85c) parameters description test conditions (1) min. typ max. units f out output frequency using crystal 10 50 mhz external clock (2) 0 100 t dc output duty cycle @ v ddo /2 47 55 % rms random rms phase jitter 25mhz @ integration range 100hz - 1mhz 0.096 @1.8v ps t r /t f clkn rise/fall time 20% to 80% 150 800 ps t sk(o) (3) output to output skew between any two outputs of the same device @ same transition @v ddo /2 80 ps t dis, t en ( 4) output enable/disable @v ddo\ /2 4 cycles notes: 1. unless noted otherwise, all parameters are tested with xtal @ f <= fxtal_max,; outputs are terminated @ 50? to v ddo /2 , see waveforms. 2. external clock source is driving xt al_in input 3. identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 4. these parameters are guaranteed, but not tested. max delay is 4 cycles. min. setup time = 3ns. 10-0151
7 ps9038c 06/29/10 PI6C10806B 1.8v/2.5v/3.3v, 100mhz, low skew 1:6 crystal to lvcmos clock buffer ac characteristics (v dd = 3.3v5%, v ddo = 2.5v5%, t a = -40c to 85c) symbols parameters test conditions (1) min. typ max. units f max output frequency using exter- nal crystal 10 50 mhz using ex- ternal clock source (2) dc 100 mhz odc output duty cycle 48 52 % t sk(o) (3) otuput skew (2) (4) 80 ps t jit(?) rms phase jitter (random) 25mhz @ integration range: 100hz-1mhz 0.091 ps t r /t f output rise/ fall time 20% to 80% 200 800 ps t en (4) output enable time (3) enable1 4 cycles enable2 4 cycles t dis output disable time (3) enable1 4 cycles enable2 4 cycles notes: 1. unless noted otherwise, all parameters are tested with xtal @ f <= fxtal_max,; outputs are terminated @ 50? to v ddo /2 , see waveforms. 2. external clock source is driving xt al_in input 3. identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 4. these parameters are guaranteed, but not tested. max delay is 4 cycles. min. setup time = 3ns. 10-0151
8 ps9038c 06/29/10 PI6C10806B 1.8v/2.5v/3.3v, 100mhz, low skew 1:6 crystal to lvcmos clock buffer ac characteristics (v dd = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c) symbols parameters test conditions (1) min. typ max. units f max output frequency using exter- nal crystal 10 50 mhz using ex- ternal clock source (2) dc 100 mhz odc output duty cycle 48 52 % t sk(o) (3) otuput skew (2) (4) 80 ps t jit(?) rms phase jitter (random) 25mhz @ integration range: 100hz-1mhz 0.122 ps t r /t f output rise/ fall time 20% to 80% 200 900 ps t en (4) output enable time (3) enable1 4 cycles enable2 4 cycles t dis output disable time (3) enable1 4 cycles enable2 4 cycles notes: 1. unless noted otherwise, all parameters are tested with xtal @ f <= fxtal_max,; outputs are terminated @ 50? to v ddo /2 , see waveforms. 2. external clock source is driving xt al_in input 3. identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 4. these parameters are guaranteed, but not tested. max delay is 4 cycles. min. setup time = 3ns. 10-0151
9 ps9038c 06/29/10 PI6C10806B 1.8v/2.5v/3.3v, 100mhz, low skew 1:6 crystal to lvcmos clock buffer ac characteristics (v dd = 2.5v5%, v ddo = 1.8v0.2v, t a = -40c to 85c) symbols parameters test conditions min. typ max. units f max output frequency using exter- nal crystal 10 50 mhz using ex- ternal clock source (1) dc 100 mhz odc output duty cycle 47 53 % t sk(o) otuput skew (2) (4) 80 ps t jit(?) rms phase jitter (random) 25mhz @ integration range: 100hz-1mhz 0.131 ps t r /t f output rise/ fall time 20% to 80% 200 900 ps t en output enable time (3) enable1 4 cycles enable2 4 cycles t dis output disable time (3) enable1 4 cycles enable2 4 cycles notes: all parameters measured at ?=f max using a crystal input unless noted otherwise. outputs are terminated at 50? to v ddo /2. 1. xt al_in can be overdriven relatively to a signal a crystal provides. 2. defned as skew between outputs at the same supply voltage and with equal load conditions. measured at v ddo /2. 3. these parameters are guaranteed, but not tested. 4. this parameter is defned in accordance with jedec standard 65. 10-0151
10 ps9038c 06/29/10 PI6C10806B 1.8v/2.5v/3.3v, 100mhz, low skew 1:6 crystal to lvcmos clock buffer jitter (typical phase noise at 25mhz) 2.5v core/2.5v output rms phase jitter (random) 100hz to 1mhz =0.112ps (typical) 3.3v core/3.3v output rms phase jitter (random) 100hz to 1mhz =0.098ps (typical) 10-0151
11 ps9038c 06/29/10 PI6C10806B 1.8v/2.5v/3.3v, 100mhz, low skew 1:6 crystal to lvcmos clock buffer waveforms bclk5 bclk[0:4] enable2 enable1 output to output skew C t sk (o) bclkx v oh v ddo /2 v ol t sk(o) bclky v oh v ddo /2 v ol t sk(o) t pzl v ddo /2 0v t pw v ddo t period t dc = (t pw / t period ) x 100% duty cycle C t dc enable1, enable2 timing diagram z = 50-ohm scope 50- ohm v ddo gnd v dd [+v ddo /2] [-v ddo /2] [v dd - v ddo /2] ac test circuit load note: v dd /v ddo = 1.8v 0.2v, 2.5v 5%, 3.3v 5% crystal characteristic (link to "http://www.pericom.com/saronix" for more detailed crystal specifcations) parameters description min typ max. units osc m o de mode of oscillation fundamental fr e q frequency 10 25 50 mhz e sr (1) equivalent series resistance 30 50 ohm c l o ad load capacitance 18 pf c s hunt shunt capacitance 7 pf d riv e level 1 mw note: 1. esr value is dependent upon frequency of oscillation 10-0151
12 ps9038c 06/29/10 PI6C10806B 1.8v/2.5v/3.3v, 100mhz, low skew 1:6 crystal to lvcmos clock buffer application notes crystal circuit connection the following diagram shows PI6C10806B crystal circuit connection with a parallel crystal. for the c l =18pf crystal, it is suggested to use c1=15pf, c2=15pf. c1 and c2 can be adjusted to fne tune to the target ppm of crystal oscillator according to different board layouts. r1 is not recommended. c1 15pf crystal?(c l? =?18pf) c2 15pf 0? r1 xtal_in xtal_out crystal oscillator circuit 10-0151
13 ps9038c 06/29/10 PI6C10806B 1.8v/2.5v/3.3v, 100mhz, low skew 1:6 crystal to lvcmos clock buffer PI6C10806B ordering information (1,2,3) ordering code package code package description PI6C10806Ble l pb-free and green 16-pin 173-mil tssop notes: 1. thermal characteristics can be found on the company web site at www .pericom.com/packaging/ 2. e = pb-free and green 3. x suffx = tape/reel pericom semiconductor corporation ? 1-800-435-2336 ? www .pericom.com 1 description: 16-pin, 173-mil wide, tssop package code: l document control no. pd - 1310 revision: e date: 03/09/05 note: 1. package outline exclusive of mold flash and metal burr 2. controlling dimentions in millimeters 3. ref: jedec mo-153f/ab pericom semiconductor corporation 3545 n. 1st street, san jose, ca 95134 1-800-435-2335 ? www.pericom.com .193 .201 .047 max. .002 .006 seating plane .0256 bsc .018 .030 .004 .008 .252 bsc 1 16 .169 .177 0.05 0.15 6.4 0.45 0.75 0.09 0.20 4.3 4.5 1.20 4.9 5.1 0.65 0.19 0.30 .007 .012 note: ? for latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 10-0151

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